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 NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
Rev. 03 -- 28 August 2009 Product data sheet
1. General description
The NX3L2T66 provides two low-ohmic single pole single throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When pin nE is LOW, the analog switch is turned off. Schmitt-trigger action at the enable input (nE) makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 1.4 V to 4.3 V. A low input voltage threshold allows pin nE to be driven by lower level logic signals without a significant increase in supply current ICC. This makes it possible for the NX3L2T66 to switch 4.3 V signals with a 1.8 V digital controller, eliminating the need for logic level translation. The NX3L2T66 allows signals with amplitude up to VCC to be transmitted from nY to nZ; or from nZ to nY. Its low ON resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and distortion of transmitted signals.
2. Features
I Wide supply voltage range from 1.4 V to 4.3 V I Very low ON resistance (peak): N 1.6 (typical) at VCC = 1.4 V N 1.0 (typical) at VCC = 1.65 V N 0.55 (typical) at VCC = 2.3 V N 0.50 (typical) at VCC = 2.7 V N 0.50 (typical) at VCC = 4.3 V I High noise immunity I ESD protection: N HBM JESD22-A114E Class 3A exceeds 7500 V N MM JESD22-A115-A exceeds 200 V N CDM AEC-Q100-011 revision B exceeds 1000 V I CMOS low-power consumption I Latch-up performance exceeds 100 mA per JESD 78 Class II Level A I 1.8 V control logic at VCC = 3.6 V I Control input accepts voltages above supply voltage I Very low supply current, even when input is below VCC I High current handling capability (350 mA continuous current under 3.3 V supply) I Specified from -40 C to +85 C and from -40 C to +125 C
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
3. Applications
I Cell phone I PDA I Portable media player
4. Ordering information
Table 1. Ordering information Package Temperature range Name NX3L2T66GT NX3L2T66GD NX3L2T66GM -40 C to +125 C -40 C to +125 C -40 C to +125 C XSON8 Description plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm Version SOT833-1 SOT996-2 SOT902-1 Type number
XSON8U plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
5. Marking
Table 2. Marking codes[1] Marking code DOO DOO DOO Type number NX3L2T66GT NX3L2T66GD NX3L2T66GM
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
1Y
1Z
1E
2Z
2Y
Y
Z
2E E
001aag497 001aah372
Fig 1.
Logic symbol
Fig 2.
Logic diagram (one switch)
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
2 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
7. Pinning information
7.1 Pinning
NX3L2T66
1Y 1 8 VCC
NX3L2T66
1Y 1Z 1 2 3 4 8 7 6 5 VCC 1E 2Z 2Y
1Z
2
7
1E
2E
3
6
2Z 2E
GND
4
5
2Y
GND
001aaj083
001aaj536
Transparent top view
Transparent top view
Fig 3.
Pin configuration SOT833-1 (XSON8)
Fig 4.
Pin configuration SOT996-2 (XSON8U)
NX3L2T66
terminal 1 index area 1E 1 VCC 8
7
1Y
2Z
2
6
1Z
2Y
3 4
5
2E
GND
001aaj084
Transparent top view
Fig 5.
Pin configuration SOT902-1 (XQFN8U)
7.2 Pin description
Table 3. Symbol 1Y, 2Y 1Z, 2Z GND 1E, 2E VCC Pin description Pin SOT833-1 and SOT996-2 1, 5 2, 6 4 7, 3 8 SOT902-1 7, 3 6, 2 4 1, 5 8 independent input or output independent input or output ground (0 V) enable input (active HIGH) supply voltage Description
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
3 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
8. Functional description
Table 4. Input nE L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table[1] Switch OFF-state ON-state
9. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VSW IIK ISK ISW Parameter supply voltage input voltage switch voltage input clamping current switch clamping current switch current VI < -0.5 V VI < -0.5 V or VI > VCC + 0.5 V VSW > -0.5 V or VSW < VCC + 0.5 V; source or sink current VSW > -0.5 V or VSW < VCC + 0.5 V; pulsed at 1 ms duration, < 10% duty cycle; peak current Tstg Ptot
[1] [2] [3]
Conditions enable input nE
[1] [2]
Min -0.5 -0.5 -0.5 -50 -
Max +4.6 +4.6 50 350 500
Unit V V mA mA mA mA
VCC + 0.5 V
storage temperature total power dissipation Tamb = -40 C to +125 C
[3]
-65 -
+150 250
C mW
The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not exceed 4.6 V. For XSON8, XSON8U and XQFN8U packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6. VCC VI VSW Tamb t/V
[1]
Recommended operating conditions Conditions enable input nE
[1]
Symbol Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate
Min 1.4 0 0 -40 -
Typ -
Max 4.3 4.3 VCC +125 200
Unit V V V C ns/V
VCC = 1.4 V to 4.3 V
[2]
To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels.
[2]
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
4 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
11. Static characteristics
Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions Min VIH HIGH-level input voltage VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V VIL LOW-level input voltage VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V II input leakage current OFF-state leakage current ON-state leakage current enable input nE; VI = GND to 4.3 V; VCC = 1.4 V to 4.3 V nY port; see Figure 6 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V nZ port; see Figure 7 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V 5 10 50 50 500 500 nA nA 5 10 50 50 500 500 nA nA 0.9 0.9 1.1 1.3 1.4 25 C Typ Max 0.3 0.4 0.4 0.5 0.6 -40 C to +125 C Min 0.9 0.9 1.1 1.3 1.4 Max Max (85 C) (125 C) 0.3 0.4 0.4 0.5 0.6 0.5 0.3 0.3 0.4 0.5 0.6 1 V V V V V V V V V V A Unit
IS(OFF)
IS(ON)
ICC
supply current VI = VCC or GND; VSW = GND or VCC VCC = 3.6 V VCC = 4.3 V 2.0 0.35 7.0 2.5 50 1.0 35 110 100 150 4.0 0.7 10.0 4.0 200 690 800 7 1 15 5 300 6000 7000 7 1 15 5 500 nA nA A A A A nA pF pF pF
ICC
additional VSW = GND or VCC supply current VI = 2.6 V; VCC = 4.3 V VI = 2.6 V; VCC = 3.6 V VI = 1.8 V; VCC = 4.3 V VI = 1.8 V; VCC = 3.6 V VI = 1.8 V; VCC = 2.5 V
CI CS(OFF) CS(ON)
input capacitance OFF-state capacitance ON-state capacitance
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
5 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
11.1 Test circuits
VCC VIL nE nZ GND nY VIH IS
VO VI
VCC nE nZ GND nY
IS
VI
VO
001aaj221
001aaj222
VI = 0.3 V or VCC - 0.3 V; VO = VCC - 0.3 V or 0.3 V.
VI = 0.3 V or VCC - 0.3 V; VO = open circuit.
Fig 6.
Test circuit for measuring OFF-state leakage current
Fig 7.
Test circuit for measuring ON-state leakage current
11.2 ON resistance
Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15. Symbol RON(peak) Parameter ON resistance (peak) Conditions VI = GND to VCC; ISW = 100 mA; see Figure 8 VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 4.3 V RON ON resistance mismatch VI = GND to VCC; between channels ISW = 100 mA VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 4.3 V
[2]
-40 C to +85 C Min Typ[1] Max
-40 C to +125 C Min Max
Unit
-
1.6 1.0 0.55 0.5 0.5
3.7 1.6 0.8 0.75 0.75
-
4.1 1.7 0.9 0.9 0.9

-
0.04 0.04 0.02 0.02 0.02
0.3 0.2 0.08 0.075 0.075
-
0.3 0.3 0.1 0.1 0.1

NX3L2T66_3
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Product data sheet
Rev. 03 -- 28 August 2009
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NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
Table 8. ON resistance ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15. Symbol RON(flat) Parameter Conditions
[3]
-40 C to +85 C Min Typ[1] Max
-40 C to +125 C Min Max
Unit
ON resistance (flatness) VI = GND to VCC; ISW = 100 mA VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 4.3 V
-
1.0 0.5 0.15 0.13 0.2
3.3 1.2 0.3 0.3 0.4
-
3.6 1.3 0.35 0.35 0.45

[1] [2] [3]
Typical values are measured at Tamb = 25 C. Measured at identical VCC, temperature and input voltage. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature.
11.3 ON resistance test circuit and graphs
1.6 RON () 1.2 VSW
(1)
001aag564
VCC VIH nE nZ GND nY
0.8
(2) (3)
0.4
(4)
(5)
(6)
VI
ISW
0 0
001aaj223
1
2
3
4 VI (V)
5
RON = VSW / ISW.
(1) VCC = 1.5 V. (2) VCC = 1.8 V. (3) VCC = 2.5 V. (4) VCC = 2.7 V. (5) VCC = 3.3 V. (6) VCC = 4.3 V. Measured at Tamb = 25 C.
Fig 8.
Test circuit for measuring ON resistance
Fig 9.
Typical ON resistance as a function of input voltage
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
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NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
1.6 RON () 1.2
001aag565
1.0 RON () 0.8
(1) (2) (3) (4)
001aag566
0.6 0.8
(1) (2) (3) (4)
0.4
0.4 0.2
0 0 1 2 VI (V) 3
0 0 1 2 VI (V) 3
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 10. ON resistance as a function of input voltage; VCC = 1.5 V
Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V
1.0 RON () 0.8
001aag567
1.0 RON () 0.8
001aag568
0.6
(1) (2) (3) (4)
0.6
(1) (2) (3) (4)
0.4
0.4
0.2
0.2
0 0 1 2 VI (V) 3
0 0 1 2 VI (V) 3
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 12. ON resistance as a function of input voltage; VCC = 2.5 V
Fig 13. ON resistance as a function of input voltage; VCC = 2.7 V
NX3L2T66_3
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Product data sheet
Rev. 03 -- 28 August 2009
8 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
1.0 RON () 0.8
001aag569
1.0 RON () 0.8
001aaj896
0.6
(1) (2) (3) (4)
0.6
(1) (2) (3) (4)
0.4
0.4
0.2
0.2
0 0 1 2 3 VI (V) 4
0 0 1 2 3 4 VI (V) 5
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V
Fig 15. ON resistance as a function of input voltage; VCC = 4.3 V
12. Dynamic characteristics
Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17. Symbol Parameter Conditions Min ten enable time nE to nZ or nY; see Figure 16 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V tdis disable time nE to nZ or nY; see Figure 16 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V
[1]
25 C Typ[1] Max
-40 C to +125 C Min Max (85 C) Max (125 C)
Unit
-
35 28 20 18 18
49 40 30 28 28
-
53 43 32 30 30
57 48 35 32 32
ns ns ns ns ns
-
32 23 14 11 11
70 55 25 20 20
-
80 60 30 25 25
90 65 35 30 30
ns ns ns ns ns
Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
9 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
12.1 Waveform and test circuits
VI nE input GND
ten tdis
VM
nY output OFF to HIGH HIGH to OFF
VOH
VX
VX
GND
switch disabled switch enabled switch disabled
001aah376
Measurement points are given in Table 10. Logic level: VOH is the typical output voltage level that occurs with the output load.
Fig 16. Enable and disable times Table 10. VCC 1.4 V to 4.3 V Measurement points Input VM 0.5VCC Output VX 0.9VOH
Supply voltage
VCC nE nY/nZ nZ/nY
G
VI
V
VO
RL
CL
VEXT = 1.5 V
001aaj224
Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times.
Fig 17. Load circuit for measuring switching times Table 11. VCC 1.4 V to 4.3 V Test data Input VI VCC tr, tf 2.5 ns Load CL 35 pF RL 50
Supply voltage
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(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
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NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf 2.5 ns. Symbol Parameter THD total harmonic distortion Conditions Min fi = 20 Hz to 20 kHz; RL = 32 ; see Figure 18 VCC = 1.4 V; VI = 1 V (p-p) VCC = 1.65 V; VI = 1.2 V (p-p) VCC = 2.3 V; VI = 1.5 V (p-p) VCC = 2.7 V; VI = 2 V (p-p) VCC = 4.3 V; VI = 2 V (p-p) f(-3dB) iso Vct -3 dB frequency response isolation (OFF-state) crosstalk voltage RL = 50 ; see Figure 19 VCC = 1.4 V to 4.3 V fi = 100 kHz; RL = 50 ; see Figure 20 VCC = 1.4 V to 4.3 V between digital inputs and switch; fi = 1 MHz; CL = 50 pF; RL = 50 ; see Figure 21 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V Xtalk crosstalk between switches; fi = 100 kHz; RL = 50 ; see Figure 22 VCC = 1.4 V to 4.3 V Qinj charge injection fi = 1 MHz; CL = 0.1 nF; RL = 1 M; Vgen = 0 V; Rgen = 0 ; see Figure 23 VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.3 V
[1] fi is biased at 0.5VCC.
[1] [1] [1] [1]
25 C Typ 0.15 0.10 0.02 0.02 0.02 60 -90 Max -
Unit
-
% % % % % MHz dB
-
0.2 0.2
-
V V
-
-90
-
dB
-
3 3 3 3 6
-
pC pC pC pC pC
12.3 Test circuits
VCC VIH nE nY/nZ nZ/nY 0.5VCC
RL
fi
D
001aaj225
Fig 18. Test circuit for measuring total harmonic distortion
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
11 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
VCC VIH nE nY/nZ
0.5VCC
RL
nZ/nY
fi
dB
001aaj226
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB.
Fig 19. Test circuit for measuring the frequency response when channel is in ON-state
0.5VCC VIL nE
VCC
0.5VCC
RL
RL
nY/nZ
nZ/nY
fi
dB
001aaj227
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
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NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
VCC nE nY/nZ nZ/nY
G
VI
RL
RL
CL
V
VO
0.5VCC
0.5VCC
001aaj228
a. Test circuit
logic input (nE)
off
on
off
VO
Vct
001aaj231
b. input and output pulse definitions Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
0.5VCC VIH 1E 1Y or 1Z
fi 50 RL
1Z or 1Y CHANNEL ON
CL 50 pF
V
VO1
0.5VCC VIL 2E 2Z or 2Y CHANNEL OFF
CL 50 pF RL
2Y or 2Z
Ri 50
V
VO2
001aah382
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 22. Test circuit for measuring crosstalk between switches
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
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NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
VCC nE nY/nZ nZ/nY Rgen
G
VI
V
VO
RL
CL
Vgen GND
001aaj229
a. Test circuit
logic input (nE)
off
on
off
VO
VO
001aaj232
b. Input and output pulse definitions
Definition: Qinj = VO x CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
NX3L2T66_3
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Product data sheet
Rev. 03 -- 28 August 2009
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NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
13. Package outline
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1
1
2
3
b 4 4x L
(2)
L1
e
8 e1
7 e1
6 e1
5
8x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07
Fig 24. Package outline SOT833-1 (XSON8)
NX3L2T66_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
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NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A1
detail X terminal 1 index area e1 L1
1
e
b
4
v w
M M
CAB C
C y1 C y
L2
L
8 5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT996-2
REFERENCES IEC --JEDEC JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-12-18 07-12-21
Fig 25. Package outline SOT996-2 (XSON8U)
NX3L2T66_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
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NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D terminal 1 index area
B
A
E
A A1
detail X
L1 L
e
4
e v M C A B w M C
5
C y1 C y
3
metal area not for soldering
2 6
b
e1
e1
7 1
terminal 1 index area
8
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05
OUTLINE VERSION SOT902-1
REFERENCES IEC --JEDEC MO-255 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-11-25 07-11-14
Fig 26. Package outline SOT902-1 (XQFN8U)
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Product data sheet
Rev. 03 -- 28 August 2009
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NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
14. Abbreviations
Table 13. Acronym CDM CMOS ESD HBM MM Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model
15. Revision history
Table 14. Revision history Release date 20090828 Data sheet status Product data sheet Change notice Supersedes NX3L2T66_2 Document ID NX3L2T66_3 Modifications: NX3L2T66_2 NX3L2T66_1
* *
Figure 6 "Test circuit for measuring OFF-state leakage current" updated. Table 8 "ON resistance": RON(flat) values for VCC = 4.3 V updated. Product data sheet Product data sheet NX3L2T66_1 -
20090420 20081204
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
18 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NX3L2T66_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 28 August 2009
19 of 20
NXP Semiconductors
NX3L2T66
Dual low-ohmic single-pole single-throw analog switch
18. Contents
1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveform and test circuits . . . . . . . . . . . . . . . 10 Additional dynamic characteristics . . . . . . . . . 11 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 August 2009 Document identifier: NX3L2T66_3


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